Ex-Huawei team design chip to speed up Hyperledger Fabric blockchain
Yesterday Accelor came out of stealth mode to reveal it has designed a new chip to speed up the Hyperledger Fabric blockchain and provide additional security. The company claims that with its chips it’s possible to achieve 200,000 transactions per second. The announcement mentioned the founders are a team of industry heavyweights from Qualcomm, Nvidia and AMD. Their résumés are impressive, but the statement omitted the fact that all three founders left Huawei in July 2018 to found Accelor.
It’s a sensitive issue given the controversial claims made about Huawei by the FBI.
The San Fransisco company also announced $2 million in seed backing from Chengwei Capital, which usually focuses on the Chinese market.
Bitcoin miners have used “ASICS” chips for a few years, with specialist hardware built by companies such as Bitmain and Bitfury. ASICS stands for Application-specific integrated circuit, and every blockchain has distinct characteristics. Doubtless, this was the spark for the idea to create new chip designs targeted at Hyperledger Fabric. However, the Accelor chips don’t appear to be ASICS. They’re FPGA which carry some risks. We’ll come back to that.
“Blockchain has introduced valuable new techniques for how we share and secure private data, but the industry’s software has run up against an impossible triangle between decentralization, security, and performance,” said GJ Chu, Co-founder, Accelor.
“Blockchain applications currently operate on top of retrofitted legacy hardware that relies on a ‘security by patch’ process and is unsuited to the rigorous computation demanded by decentralized protocols. Commodity CPUs are not friendly to the cryptographic, network, and database operations necessary for these systems to scale without sacrificing security and it is paramount for the industry to move these intensive computing functions onto dedicated hardware.”
Accelor has two aspects to its design. The Accelor Performance Engine (APE) is the part that speeds up the cryptography and other processes to deliver 10x greater throughput compared to software-only solutions.
Additionally, the Accelor Security Architecture (ASA) aims to address current security issues. In the past few years there have been some serious CPU-based vulnerabilities – Spectre, Meltdown, and Foreshadow – which have meant that data that should not be accessible within the CPU potentially could be snooped. The operating system companies have introduced patches to protect users. Accelor asserts that these issues have impacted Trusted Execution Environments, a ring-fenced part of processors, which are usually used to protect cryptographic keys.
The Accelor statement says that “ASA leverages an FPGA-based confidential computing model that gives users ultimate authority over their hardware, affording each individual the flexibility to choose where to place their root of trust, thereby achieving a more decentralized hardware solution.”
An FPGA is a field-programmable gate array, which means that users can reprogram the circuits. The U.S. Department of Defense states that the “Programmable nature of FPGAs and System on Chips (SOCs) make them vulnerable to cyber malware and malicious insertion.” Others have outlined the security issues here and here. This compares to ASICS which are usually mass produced with the code permanently written to the chip to make them harder to tamper with. And ASICS are much faster than FPGAs.
In Accelor’s press announcement, Dr. Larry Shi outlined the benefits of the chips. He’s the Head of the Blockchain Research Team at the University of Houston (UH), and Senior Member of the Institute of Electrical and Electronics Engineers (IEEE).
“Accelor’s confidential computing architecture has three key advantages to deliver a higher standard in trusted computing. Clients have more freedom to manage their devices, such as setting up their own identity management systems to authenticate each device under their control,” he said.
“FPGAs are faster and have greater power efficiency than general purpose processors for computationally intensive tasks such as expensive zero-knowledge proof related operations. Lastly, FPGAs are already widely used in the IoT and embedded systems market.”